Field of the Invention
The invention relates to a semiconductor structure. More particularly, to a semiconductor structure with stepped conductive vias.
Description of Related Art
Recently, along with the rapid development of electronic technologies and the semiconductor industry, electronic products that are more user-friendly and with better performance are continuously placed in the market, and these products are designed to be lightweight and more compact than before. Due to present wafers, semiconductor devices or circuit boards all aiming at being implemented toward high integration, a line width between internal integrated circuits becomes smaller and smaller and even achieves a nano-size degree. However, a size of a conductive via is also restricted while the line width becomes smaller, which brings a great challenge to the manufacturing process of conductive vias with greater depths.
Moreover, as a material (e.g., copper) of conductive wires and the conductive vias has unsatisfactory engagement with a dielectric material having a low dielectric constant, a phenomenon of delamination, damage or crack, for example, sometimes occurs between the conductive wires and the dielectric material. In addition, due to the presence of coefficient difference of thermal expansion (CTEs) between the dielectric material and the conductive material, the engagement of the dielectric material and the conductive material is easily damaged by thermal stress and results in a warpage or delamination phenomenon, which leads to the reduction in reliability and life span of the semiconductor structure.